1. Field of the Invention
The present invention relates to test handling methods and equipment for conjoined integrated circuit dies.
2. Background Information
A plastic, integrated circuit housing is conventionally injection molded about an integrated circuit chip mounted to a substrate to form an integrated circuit package that may measure 1 xc2xd inches by 1 xc2xd inches. A trend in the integrated circuit packaging industry has been to scale the integrated circuit package to the size of the chip or xe2x80x9cdiexe2x80x9d contained therewithin by eliminating the need to encapsulate the chip within a plastic housing on a substrate. This is accomplished by attaching interposers of ceramic, organic laminates, or, preferably, flexible polyamide films to the exposed circuit pattern on the bottom of a flip chip. The resulting product, known as a Chip Scale Package when singulated, minimizes package parasitics and permits shorter, finer trace lines while eliminating the flip chip need of an underfill step after assembly. U.S. Pat. Nos. 5,684,330, 5,714,800, and 5,814,894 relate to different Chip Scale Packages.
The flexible, polyamide film used to produce a Chip Scale Package (CSP) such as a Microball Grid Array (xcexcBGA) may be a long, three-layer (one-metal layer) flexible interposer tape 10 as shown in FIG. 1. The three layers of tape 10 consist of rolled copper layer 12 laminated to polymer film 14 with a layer of adhesive 16. Following lamination, adhesive 16 is cured. Flexible interposer tape 10 has sprocket holes 18 and matrix holes 19 distributed along the length of tape 10. Sprocket holes 18 receive toothlike projections arranged on a wheel rim to urge tape 10 forward during handling. Matrix holes 19 are discussed below.
A plurality of uniformly spaced device sites or lead patterns 20 are photolithographically defined on copper layer 12 into a matrix having a particular pitch to allow for efficient material handling. As illustrated by example in FIG. 2, the lead pattern 20 matrix is etched to form land pads 22 on circuit side 24 that are complimentary to matrix holes 19 of FIG. 1. Land pads 22 permit the deposition of bumps by solder ball placement ultimately to populate die 44 (FIG. 4) with solder balls to form a complete CSP. The lead pattern 20 matrix also is connected to lead beams 26 on chip side 28 through a combination of traces 30 and through holes 31 that run through the thickness of copper layer 12. Subsequently, land pads 22, traces 30, through holes 31, and lead beams 26 are plated with a thin layer of gold or electroless tin. FIG. 3 shows plated land pads 22 as exposed for access at circuit side 24 through matrix holes 19 of interposer tape 10.
To mass produce CSPs, a low viscosity, low stress adhesive 42 of FIG. 4 is dispensed onto chip side 28 of interposer tape 10. Adhesive 42 aids in coupling chip 44 to interposer tape 10. Arranged around the perimeter of each chip 44 is In Puts/Out Puts (I/Os) 48. Each chip 44 is picked and placed about lead beams 26 of one lead pattern 20. Bonding wires 46 are arranged between gold plated, copper lead beams 26 and In Puts/Out Puts (I/Os) 48 of the associated individual chip 44 and bonded thereto through sonic waves as shown in FIG. 4. The sonic wave bonding process electrically interconnects each chip 44 to the flexible interposer tape 10 as well as mechanically interconnects each chip 44 to the flexible interposer tape 10 by curing the low stress adhesive 42. Chip side 28 of interposer tape 10 is then coated with encapsulant 36 to seal the remaining exposed metal trances 30 on chip side 28 and to provide a die edge bumper to prevent the die from cracking during handling.
The long length of flexible interposer tape 10 having a matrix of interconnected dies is then segmented into strips or panels 32. FIG. 5 shows a three row, sixteen column matrix. Segmented panel 32 may then be mounted on aluminum carrier frame 34 using a heat sensitive tape such as tape 38 shown in FIG. 6. Aluminum carrier frame 34 permits standard magazine-to-magazine handling as well as permits alignment such as by alignment holes 35 and 36. Segmented panel 32 mounted to carrier frame 34 with tape 38 forms reinforced panel 48 as shown with chip side 28 facing up in FIG. 5 and with circuit side 24 facing up in FIG. 6. An example of a reinforced panel is shown in U.S. Pat. No. 5,866,949.
To conventionally test the CSP""s, the dies are populated with solder balls and cut from the segmented panel in a process known as singulation such as in U.S. Pat. No. 5,756,370, U.S. Pat. No. 5,815,000, U.S. Pat. No. 5,834,945, and U.S. Pat. No. 5,844,419. The singulated CSP""s are then tested individually, which wastes time. A more efficient technique would be to test dies 44 while mounted on reinforcing panel 48.
CSP test handling equipment is dependent on package thickness, outer dimension, pitch, pad flatness, and pad height. Thus, a critical concern in multi-unit testing of two or more dies such as might be conjoined within reinforcing panel 48 is the alignment relationship between each individual die within segmented panel 32. Moreover, because CSPs are die size, they will continue to change size both in outside dimensions and thickness. Thus, CSP test handling equipment must be flexible enough to change with the change in die size. In addition, without the protection of solder ball bumps, the land pads of each die are more sensitive to the force used to contact a prober to a pad surface. Also, since cost is usually a factor, it is important to be able to utilize existing wafer prober systems in handling and testing conjoined dies. Some of these needs are identified in Jack Kessler, Chip-Scale Packaging Final Test; The Paradigm Shift Begins, 2 Chip Scale Review 26 (May 1998), but remain unsatisfied.
What is need is test handling method and equipment for conjoined integrated circuit dies that utilize existing wafer prober systems and are sensitive enough to account for the alignment relationship between each individual die and to account for the exposed pad surface as well as flexible enough to change with the change in die size.
A test handling assembly for conjoined integrated circuit dies is disclosed. The assembly has a wafer prober system having a chuck. A panel stage is coupled to the chuck and conjoined integrated circuit dies are coupled to the panel stage. A contactor is provided to communicate with the conjoined integrated circuit dies and the wafer prober system. Other features are disclosed.